This will involve the implementation of pilot lines for integrated application-defined sensors, novel IoT solutions, complex sensor systems and new (bio)medical devices, new RF and mm-wave device options (including radar), photonics options, electronics and packaging solutions. Key will be the initiation of process technology platforms for the exploration and exploitation of advanced functionalities through integration of novel reliable materials.

The exploration and implementation of materials beyond Si will require strategic collaborative EU projects for European industry to become more independent, and will result in the development of a EU-based supply chain for wide-bandgap materials, for example, including a move towards larger substrate sizes of 200 and 300 mm (i.e. SiC and GaN).

Improved materials and assembly techniques will result in more feasible applications for large-area, lightweight, robust and structurally integrated electronics. Hybrid approaches will be used more often, and the boundaries between µ-electronics, semiconductor electronics and flexible electronics will slowly disappear. Strategies to create stretchable electronics will also be developed.

More specifically, the following challenges are identified (this is a non-exhaustive list).

Application-specific logic: as explicitly treated in sub-section 1.1.4.3, heterogeneous SoC integration can require specific solutions for logic to be integrated with more-than-Moore technologies such as the following:

• Tight logic/memory integration for new architectures for neuromorphic computing.

• Logic integration with RF, optical or sensor technologies.

• Ultra-low power (ULP) technology platform and design.

• Integration of lasers and detectors within silicon photonics platform.

Advanced sensor technologies:

• Mechanical sensors (e.g. acceleration, gyroscopes, microphones).

• Chemical sensor devices such as selective gas-sensing components for environmental monitoring or smart medicine and smart health (e.g. CO, CO₂, NO_x, O₃, toluene, VOCs, acetone, H₂S).

• Physical sensors (magnetic, optical, RF).

• Multispectral or highly sensitive optical sensors

• Transmitter/receiver technologies for applications such as lidar and active phased array imaging.

• Biomedical and biochemical sensors.

Quantum sensor technologies:

• Atomic vapor or cold atom (Bose-Einstein condensate) based sensors

• Trapped ion based quantum sensors

• Solid state spin based quantum sensors making use of Nitrogen-Vacancies or color centres as sensitive element

• Superconducting circuit sensors based on SQUIDS, flux qubits and charge qubits

• Sensors based on photon entanglement using nonlinear optical media

Advanced power electronics technologies (Si-based, BCD, SiC, GaN, Ga₂O₃, AlN etc.) to enhance the efficiency of motors, energy storage, lighting systems, etc. More specifically:

• Higher power density and frequency, wide-bandgap materials for high temperature electronics, new CMOS/IGBT processes, integrated logic, uni- and bipolar; high voltage classes, lateral to vertical architectures.

• Materials for energy harvesting (e.g. perovskite solar cells, piezoelectric ceramics and thin films) and storage (e.g. perovskites, ferroelectrics and relaxors), micro-batteries, supercapacitors and wireless power transfer.

• Power devices and modules for highly demanding automotive, industrial and energy infrastructure applications.

• Substrates towards larger diameters to serve future greater demand for cost-sensitive power solutions.

Advanced RF and photonics communication technologies to interface between semiconductors components, subsystems and systems. These technologies should enable better and more energy-efficient control of emission and reception channels (for example, for 5G connectivity and 6G preparations) via:

• New energy-efficient RF and mm-wave integrated device options, including radar (building on e.g. SiGe/BiCMOS, FD SOI, CMOS, GaN, III-V, PIC).

• Development and characterisation of new RF cryogenic electronics for QIP, as well as logic devices at quantum-enabling cryogenic temperatures taking into account the available cooling power of refrigerators and interfacing requirements at different operation temperatures.

• Energy-efficient computing and communication, including a focus on developing new technologies.

• Bringing MOEMS and micro-optics, nanophotonics, optical interconnections, photonics-enabled device and system options into a CMOS-compatible manufacturing and/or packaging flow.

• Integration of solid-state light emitters such as LED and laser with, or onto, a CMOS-compatible platform.

Electronics on flexible and structural substrates are to a large extent dealt with in the Chapter 1.2 on Components, Modules and Systems Integration. However, specific aspects related to process technology are also required:

• Development of new process capabilities for adapting to flexible, structurally integrated and stretchable electronics, which includes enabling large interconnection areas on substrates.

• Novel (semi)conducting, insulating and encapsulation materials for more reliable devices, and novel substrate materials that can deal with the challenges of flexible electronics.

• Flexible electronics is prone to be used as disposable electronics, and therefore biodegradable materials should be developed that can demonstrate the required performance.

Over the last few years a huge variety of semiconductor products have emerged where several functions are added in one IC package, enabled by advances in integration and packaging technology.

To maximise the benefits from ICs made for IC-nodes of 7 nm and less, there has already been a move from simple wire bonding to more advanced methods such as ball grid arrays (BGAs), flip chips, wafer-level packaging, fan-out wafer-level packages without substrate interposers and complex 3D structures with TSVs, micro-bumps and thin dies.

The functional diversification of technologies, where digital electronics meets areas such as analogue, photonic and MEMS technologies, has been advanced through the assembly/packaging of heterogeneous elements. For example, in today’s power stages in automotive powertrain applications, there could be power modules that integrate several dies in parallel. Similarly, 5G networks are enabled by advanced RF functionality, often combining a photonic interface with in-package integrated logic and memory functionalities. Upscaling of capacity for photonic ICs may be kickstarted via microwave photonics as a new domain. Semiconductor materials in packaging technology have already moved from being largely silicon-based to more advanced SiC and GaN compounds, as well as towards environmentally friendly lead (Pb) and halogen-free mold compounds. For wire bonding, a similar move from aluminium and gold towards copper and silver wiring has been made. Furthermore, flip chip attach has made a transition to lead-free bumps and BGA using lead-free ball materials.

This challenge covers the integration of new chip technologies in advanced low parasitic packages, as well as chips of different functionalities resulting from the previous two challenges – e.g. CMOS logic, NVM, NEMS/ MEMS, RF, analogue, sensing, actuating, energy harvesting and storage – into an SiP.

Advanced packaging technologies are required for mm-wave applications (> 30 GHz), both GaN/Si RF and other high-electron-mobility-transistor (HEMT) devices, or dedicated MEMS and sensor devices (e.g. electro-optics for lidar without moving parts). Depending on the application, heterogeneous SiP technology can provide a better compromise between available functions, performance, cost and time to market.

Assembly and packaging (A&P) technologies, especially those with a focus on system integration, are a key enabler for European industry, including the new field of cryogenic QIP, characterisation of logic devices at quantum-enabling cryogenic temperatures, and associated packaging challenges. To maintain and strengthen Europe’s position, it is necessary to improve existing technologies and develop emerging technologies, as well as to integrate both to advanced electronic systems in a competitive and reliable way. All application domains addressed by the ECS agenda will benefit from innovative assembly and packaging, including SiP components.

Moreover, component carriers also known as Integrated Circuit (IC) Substrates represent a big portion of the package cost (up to 50%), excluding the semiconductor component itself. This is particularly true for Flip Chip Ball Grid Array (FC-BGA) Substrates, which are essential component carriers in high performance computing solutions. Due to the increase of functionality and driven by chiplets integration, FC-BGA substrates are facing many challenges not only in terms of miniaturization, but also they are becoming central elements for power management in advanced computing systems.

Integration of the above functionalities in miniaturised packages and (sub)SiP require fundamental insights into application needs and system architecture. Process and characterisation technology to realise this integration is part of this third Major Challenge, and is essential for ensuring Europe’s prominent role in supplying novel solutions for the various existing and emerging application domains.

Compared to chip technology, assembly and packaging are becoming increasingly important. In many cases, assembly and packaging costs are becoming higher than the chip cost. To reverse this trend, we must focus on dedicated packaging and SiP process technologies that consider all the levels of chip, package and board/ system to identify the optimum trade-offs between function, cost, power, reliability, etc.

To remain economically sustainable and globally competitive, a toolbox must be set up, including evolution of current process technologies as well as new ones, aiming to provide cost-effective and outstanding system integration. Alternative low cost solutions are needed addressing 2.xD integration include interposers based on inorganic, e.g. Si and glass, as well as organic, e.g. FC-BGA and RDL-based, substrates. Furthermore, novel 3D interconnect solutions should be explored enabling new levels of integration for high performance and multifunctional electronic smart systems (ESS).

At the macro-scale level, a system consists of a collection of large functional blocks. These blocks have quite different performance requirements (analogue, high voltage, eNVM, advanced CMOS, fast static RAM (SRAM), multi-sensing capability, etc) and technology roadmaps. Therefore, for many applications it is of increasing interest to split the system into heterogeneous parts, each realised by optimum technologies at lower cost per function, and assembled with parts using high-density 3D interconnect processes.

It is clear that 3D integration in electronic systems can be realised at different levels of the interconnect hierarchy, each having a different vertical interconnect density. Different technologies are therefore required at different levels of this 3D hierarchy.

Research and development priorities are focused on innovative approaches, such as the following.

Advanced interconnect, encapsulation and packaging technologies:

• Interconnect technologies that allow vertical as well as horizontal integration: this includes process technologies for vertical interconnects, such as TSV, through-encapsulant via (TEV) technologies and microbumps, and copper/copper bonding, as well as process technologies for horizontal interconnects such as thin film technologies for redistribution both on chips and encapsulation materials. A technology base is needed for 3D stacking as well as horizontal interconnecting of dies and chiplets. This also includes interconnects through optical interfaces, most notably off-chip, but also within a package.

• Implementation of advanced nanomaterials and metamaterials, including low-thermal-budget-processing 2D materials, nanowires, nanoparticles and quantum dots with scalable logic and memory device technologies, which will be key for adding new functionalities and developing multifunctional smart systems.

• New materials like Al bumps from Electroplating could solve reliability issues and ensure advanced CMOS compatible packaging on Wafer level bonding and Chip Integration.

• Power electronic substrates will benefit from thick Al layers fabricated by novel electroplating technologies.

• Specific power and RF application technologies.

• Solutions for high-frequency miniaturisation, such as for mm-wave applications (> 60 GHz) and for > 100 GHz towards THz applications for which no package solutions currently exist.

• Increasing functionality in IC Substrates for high efficiency power delivery including voltage regulator circuitry and integrated capacitance. Additionally, fine structuring capability achieving high bandwidth interconnections has to be reached either sequentially (2.1D) or recombining separated manufactured carriers (2.3D and 2.5D).

3D integration technologies:

• High-integration density and performance-driven 3D integration (power/speed). For this category, denser 3D integration technologies are required: from the chip I/O-pad level 3D-SIP, to finer grain partitioning of the 3D-SOC and the ultimate transistor-level 3D-IC (see Sub-section 2.3.1 for the 3D landscape).

• Chip-package-board co-design. This will be of utmost importance for introducing innovative products efficiently with a short time to market (and which is closely linked to the work described in Section 2.2).

• System integration partitioning: the choice of 3D interconnect level(s) has a significant impact on system design and the required 3D technology, resulting in a strong interaction need between system design and technology with a significant impact on electronic design automation (EDA) tools.

Enhanced reliability, robustness and sustainability technologies:

• Solutions for high reliability, robustness and high quality. For this, a close consideration of the chip/package interaction, but also of the interaction of chip/package to the board, is required. R&D in this area requires a strong link, especially with materials and their compatibility, and also consideration of the heat dissipation challenges. In addition, variations and extremities in operating environmental conditions should be considered to ensure devices work seamlessly and operational life is not impaired. Avoiding (particle) contamination is another, increasingly critical, requirement. In the last decade nearly all assembly and packaging materials have changed; in the next 10 years, it is expected they will change again. Also, a close link with the Architecture and Design section is crucial here.

• Solutions to test separate components, before and after assembling these in a single package/ subsystem. Concepts like built-in self-test (BIST) and self-repair require some amount of logic integration, and a design providing access for die testing.

System requirements and semiconductor device technology (Major Challenges 1 and 2) will evolve at the same time, creating momentum for further interconnect pitch scaling for 3D integration technology platforms. Hence, the timelines of all four challenges of this section are strongly connected.

The ever-increasing demand for leading-edge logic and memory technology is driving the development of new equipment and material solutions for sub-2 nm node semiconductor technologies. Besides finding equipment solutions for further shrinking minimum feature sizes well below 10 nm, the alignment accuracy of successive layers, called “overlay” or in another definition type “Edge Placement Error”, needs to move towards Angstrom levels in a process technology roadmap that combines complex materials in 3D structures and architectures. At the same time, productivity demands on the equipment continue to increase to maintain reduced overall production costs. Process yield also continues to be a challenge with shrinking feature size and the increasing impact of defects and contamination.

The overarching goal of equipment development is to lead the world in miniaturisation techniques by providing appropriate products two years ahead of the shrink roadmap of world’s leading semiconductor device and components manufacturers¹³. Internationally developed roadmaps such as the International Roadmap for Devices and Systems (IRDS) will also be taken into consideration¹⁴. Currently, leading integrated device manufacturers (IDMs) are forecasting a continuation of the technology roadmap following Moore’s law at least until 2029¹⁵, which corresponds to at least four new generations after the current technology node.

These equipment solutions will enable high-volume manufacturing and fast prototyping of electronic devices in CMOS and beyond CMOS technologies, and therefore allow for supplying the world market with technology-leading, competitive products. Applying new skills and knowhow in areas such as 3D heterogeneous integration and advanced SoC solutions (covered in Major Challenges 2 and 3 of this section) will create and trigger new technological and business opportunities.

For another part of the semiconductor ecosystem, which is also a European strength, system integration equipment is required that can combine chips and wafer technologies of various wafer sizes. In the coming years, 3D integration and SOC manufacturing will add complexity to the global supply chain, and generalise the concept of distributed manufacturing. This will require the development of new concepts for information and control. The interfaces and handovers between wafer technologies and assembly and packaging need to be clearly defined, and will require innovative equipment. Such technologies will necessitate working more closely together, combining front-end wafer equipment, and assembly and packaging equipment. Technologies and methodologies that are well established for Si wafers will partially be reused and adapted for assembly and packaging.

Heterogeneous SoC and SiP integration will pose significant challenges and require R&D activities in a multitude of fields. Equipment and material research must drive the general technology trends in respect to miniaturisation and integration of more functionality into a smaller packaged IC volume, and with higher efficiency, lower power consumption and longer battery life. Processes, equipment and materials for heterogeneous integration can be partially sourced from previous-generation CMOS infrastructures. However, new technology generations will also require capabilities that are not yet available in advanced CMOS fabrication.

Today’s equipment was typically designed for the high-volume continuous production of advanced logic and memory devices, which requires major modifications or re-design when used as production tools for heterogeneous integration. Extending the life of installed equipment to match requirements of this domain via proactive lifecycle management (refurbishment) of these products will provide cost-effective solutions for specific applications. The performance must be enhanced for smaller batch production providing high flexibility and productivity at low cost of ownership.

Furthermore, the trend in solutions of ever-decreasing feature size with an ever-increasing number of features, and interconnects packed onto an IC, puts strong demands on product validation and verification methodologies, as well as on test methodologies and respective equipment.

It is imperative that the equipment and manufacturing sector enables highly flexible, cost-competitive, “green” manufacturing of semiconductor products within the European environment that enables European manufacturers to lead the evolution toward sustainable electronics. To achieve this, semiconductor manufacturing should lead the way in terms of digitisation, with a focus on secure, flexible and sustainable manufacturing and a move from “advanced process control-enabled” equipment to cyber-physical systems. The developed solutions should include innovations for resource-saving and energy-efficiency improvement, with further enhancement of productivity, cycle time, quality and yield performance, at competitive production costs. Furthermore, it will be key to adapt workflows to new, data-driven manufacturing principles adopting digital twins, AI, machine-learning and deep-learning methods, as described in Section 3.3 Digital Industry of this document.

Equipment and equipment integration need to become even smarter than it already is, carrying out intelligent data processing based on enhanced sensors and AI assisted operating strategies, not only to guarantee stable processes but also to learn, adapt and improve from data gathered and pre-processed in real time.

While the chip advancements are contributing to the industries across verticals, the increased development of chips is also adding to environmental wastes. For instance, fabricating a small 2g microchip (≈ 14-10nm technology node) requires 32-35 kilograms of water, 1.6kg of petroleum and 72g of chemicals¹⁶. Since very advanced technology nodes will require more process steps, and since the chip production could nearly double for satisfying chip demand in the coming years, the environmental impact of the semiconductor industry on power/energy and water consumption, as well as on CO₂ and GHG emission will strongly increase up to unacceptable levels to cope with the Green Deal objectives.

Like for its energy consumption, the water and carbon footprints of the semiconductor industry can be classified in three groups or ‘Scopes’:

• Scope 1: Water consumption and CO₂ emission as a direct result of the wafer fab usage.

• Scope 2: Water consumption and CO₂ emission come from purchased energy powering semiconductor fabs and their associated offices.

• Scope 3: Water consumption and CO₂ emission come from all other activities, including the full upstream and downstream supply chain.

A 2011 study¹⁷ unveils that the wafer consumption of semiconductor production lines mainly results from the wafer fab usage (Scope 1: 97.3%), while the contributions of scope 2 and 3 were minor: 2.5 and 0.2%, respectively. Each chip needs to be rinsed after many process steps with ultrapure water (UPW) to remove various debris (ions, particles, silica, etc.) from the manufacturing process and prevent the chips from becoming contaminated. It takes 1,400-1,600 litres of municipal water to make 1,000 litres of UPW. Accordingly, for economic rather than ecological reasons, the semiconductor industry has been working for more than twenty years to reduce the amount of water needed to manufacture a chip (Scope 1). To avoid discharges and possible pollution, the proportion of closed-circuit water networks in semiconductor manufacturing plants is increasing. However, the total volume of water consumed by the semiconductor industry has never decreased as the number of chips released from the plants has also exploded over time.

Nowadays, due to the more frequent occurrence of droughts, the water issue is high on the sustainable development plans of major semiconductor companies. Semiconductor manufacturers must focus their efforts on new ways to recycle, reduce, and reuse the water used in their production. Nevertheless new advancements in water treatment must emerge to allow semiconductor manufacturers to recover and reuse wastewater, remove targeted contaminants, and even reclaim valuable products from waste streams.

Indeed, the semiconductor manufacturing process uses a wide range of slurries and chemicals, including hydrofluoric acid for cleaning and etching photosensitive components following the photolithographic process. Other chemicals such as ammonium hydroxide, hydrogen peroxide, hydrochloric acid, sulfuric acid or phosphoric acid are commonly used in rinsing operations. The wastewater includes mixtures of these chemicals, together with other contaminants that result from the manufacturing processes, such as traces of nickel, copper, cobalt, titanium, fluoride, silica, ammonia, and many other organic and inorganic compounds. The complexity of the wafer fabrication processes leads to the generation of wastewater streams that are highly contaminated with chemicals and particles. The fabrication process also uses PFAs (for instance in resists, or CMP slurries). Successful treatment or reclamation of the waste streams will thus require robust effluent segregation systems, such as micro- or ultra-filtration, reverse osmosis, precipitation, flocculation, sludge and membrane bioreactor. New long-term approaches could deserve some R&D efforts for improving the effluent segregation systems and hence increasing the use of recycled water in semiconductor manufacturing lines. With about 80% of semiconductor manufacturing emissions falling into either scope 1 or scope 2 categories, fabs control a large portion of their CO₂ and Green House Gases (GHG) emission. Scope 2 emissions, which represent the highest proportion of GHG from semiconductor companies, are linked to the energy required to run their production facilities. The sources of these emissions include:

• Tool fleets containing hundreds of manufacturing tools, such as lithography equipment, ion implanters, high-temperature furnaces, deposition and etching tools, etc.

• Large clean rooms requiring climate and humidity control with overpressure and particle filtration.

• Extensive sub-fab facilities for gas abatement, exhaust pumps, water chillers, and water purification.

The energy invested in a completed device can be 5.4 MJ (1.5 kWh) or more per square centimetre¹⁸. Furthermore, the fab energy consumption is expected to rise with more advanced process technology nodes.

Compared with “brown” or fossil energy (e.g., coal, gas), “green” energy (e.g., solar, wind, hydropower, and other low carbon) produces up to 30x fewer GHG emissions¹⁹. To ensure that sufficient power is always available, fabs often source their electricity from a combination of on-grid and off-grid sources. Most current off-grid power comes from fab-owned fossil fuel power plants. Over the short term, fabs can significantly reduce the energy consumption of these plants by pursuing efficiency improvements by including battery storage or switching to alternative fuels such as biogas or green hydrogen. For on-grid power, fabs may be able to reduce emission by purchasing renewable electricity from utilities through green premium energy offerings, which are often available in Europe.

European semiconductor manufacturing lines must reduce their energy consumption for reducing their operational costs and increasing profitability, but also for decreasing their environmental impact. This can be achieved in the short or midterm by investigating, in collaboration with the equipment suppliers, the energy efficiency of each processing tool and/or by creating energy-efficient process recipes without affecting the overall equipment effectiveness.

Scope 1 emissions, which also significantly add to fab GHG emission profile, arise from process gases used during wafer etching, chamber cleaning, and other tasks. Furthermore, they rise as node size shrinks. These gases, which include PFCs, HFCs, NF₃, and N₂0, have high global-warming potentials. For instance, PFC 14, PFC16, CHF₃, NF₃ and SF₆ respectively exhibit a global warning potential of 6,500x, 9,200x, 11,700x, 17,200x and 23,500x that of CO₂. Moreover, the lifetime of such gases in the atmosphere can be very long 50,000 years, 10,000 years and 3,200 years for PFC14, PFC16 and SF₆, respectively.

In the short-term, semiconductor companies must collaborate with equipment suppliers to decrease their GHG emission and their operational costs by adjusting process parameters, such as temperature and chamber pressure, cooling water temperatures and by simultaneously optimizing yield and energy consumption during cleaning protocols.

Since much of these GHG and CO₂ emissions come from burning perfluorocarbons (PFCs), chemicals, and gases, more efficient gas abatement systems will probably be the main lever to address GHG emissions from process gases over the short to midterm.

Gas recycling of unutilized process gases and by-products through various means, such as membrane separation, cryogenic recovery, adsorption, and desorption can be a long-term approach for reducing the GHG emission. In collaboration with equipment suppliers, semiconductor fab could then refine them into pure process gases that can be used again, potentially reducing process-gas emissions. For this lever to become economically viable, collaboration between semiconductor companies, equipment suppliers and researchers will be compulsory to address these major challenges related to the separation of process-gas outflows and purification.

Another long-term approach could consist in lowering GHG emissions by switching chemicals that have a lower environmental impact than the aforementioned fluoride gases, such as on-site generation of F₂ for replacing NF₃, since molecular F₂ has no global warming potential. Nevertheless, developing new solutions will require strong R&D efforts and will be both costly and time consuming, as is the process for qualifying new chemicals on existing processes and tools.

Since most of the aforementioned fluoride compounds are used for etching, another long-term approach could concern the replacement of some non-critical etching processes by additive manufacturing process steps. Such a replacement will require strong R&D efforts to develop strongly selective deposition processes and/or self-assembled molecules that can prohibit the deposition of metal and dielectrics.

For a single phone unit, the precious metal content (without battery) is 250 mg Ag, 24 mg Au, 9 mg Pd, and 9 g Cu on average. For a single PC or laptop, the precious metal content (without battery) is 1g Ag, 220 mg Au, 80 mg Pd, and 500 g Cu on average platinum²⁰. Taking into account the average number of cell phone, and PC-laptops currently sold per year (1.5 billion and 350 million, respectively) the recycling of these electronic devices can yield to 725 tonnes Ag, 113 t Au, 42 t Pd and 189,000 t Cu per year. Increasing e-waste recycling in order to address the large environmental impact of mining the Earth for metals looks nowadays mandatory. For not wasting mineral resources in view of the limited extractable quantities of metals in the earth’s crust, chipmakers will be more and more concerned with the potential scarcity of some ores that are compulsory for producing ultra-pure metals for the high-volume manufacturing of devices. One way should be to use recycled metals instead of premium metals. Another approach for preventing the use of natural resources consists in recovering the metals for the electronic wastes (e-wastes). Since the amount of precious metal contained in a single smartphone or tablet compared to the overall weight and size is small , and therefore extremely difficult to recover from a scrapped device, the recovery of scarce metals from microelectronic devices opens a wide research domain for material scientists. Their solutions are very much needed to ensure sustainable usage of scarce metals in chip production.

Expected outcome

The goal of the European equipment and manufacturing industry for advanced semiconductor technologies is to lead the world in miniaturisation and performance by supplying new equipment and new materials approximately two years ahead of the introduction schedules for volume production of advanced semiconductor manufacturers. The focus will be on equipment and manufacturing technologies for lithography, metrology and wafer processing, including the respective infrastructure for sub-3 nm node technologies. Further focus needs to be on innovative equipment and material technologies for heterogeneous SoC and SiP integration, enabling advanced packaging of single and/or multi-node chips/chiplets.

Moreover, European semiconductor equipment and manufacturing technologies will be innovation leaders in terms of the use of AI, machine learning in the operation of semiconductor fabrication, and in taking care of limited datasets for model training in a high-mix environment. Solutions for current and future factories will allow high-productivity manufacturing of variable volume, and the energy-efficient, sustainable, resource- saving volume production of semiconductors.

The key focus areas for innovative semiconductor manufacturing equipment technologies are as follows.

Wafer fabrication equipment:

• Advanced patterning equipment for sub-2 nm node wafer processing using deep ultraviolet (DUV) and EUV lithography, and corresponding subsystems and infrastructure (e.g. pellicles, masks and resist).

• Mask manufacturing equipment for sub-2 nm node mask patterning and tuning, defect inspection and repair, metrology and cleaning.

• Advanced holistic lithography using DUV, EUV and next-generation lithography techniques, such as e-beam and mask-less lithography, directed self-assembly (DSA) and nano-imprinting.

• Multi-dimensional metrology (MDM) and inspection for sub-2 nm node devices that combine all the spectrum of physical tools and data processing techniques.

• Thin film processes including thin film and atomic layer deposition, doping and material modification, and corresponding equipment and materials, able to support the increase of binary, ternary and quaternary materials

• “Bottom up” technologies to selectively deposit materials on topography or on a selected material.

• Integrated surface preparation, deposition and etch process technologies for optimal interface engineering.

• Innovative equipment and process strategies for perfect gapfill of metals and dielectrics in decreasing feature sizes.

• Equipment and manufacturing technology for wet and dry processing, wet and dry etching, including (atomic layer) selective etch processing, thermal treatment, laser annealing and wafer preparation.

• Increased utilization of AI and modelling (e.g. computational chemistry) techniques for material and process development.

• Technologies and tools for the manufacturing and integration of semiconductor components made with advanced nanomaterials and metamaterials (low-thermal-budget-processing 2D materials, nanowires, nanoparticles, quantum dots, etc) with logic and memory technologies.

• High-volume manufacturing tools for the production of III-V, GaN, SiC or other exotic material substrates of up to 200 mm, or 300 mm in the future.

• Dedicated equipment for manufacturing of electronics on flexible, structural and/or bio- compatible substrates.

• New electroplating equipment for ionic liquids (i.e. for Al deposition).

Assembly equipment:

• Equipment and manufacturing technology supporting 3D integration and interconnect capabilities such as chip-to-wafer stacking, fan-out WLP, multi-die packaging, “2.5D” interposers, wafer-to-wafer sequential processing, TSVs and transistor stacking.

• Enhanced equipment optimised for high-volume manufacturing of large batches of the same package into efficient reconfigurable equipment for the manufacturing of different packages in smaller batches.

• New process tools for die separation, attachment, thinning, handling and encapsulation for reliable heterogeneous integration on chip and in package, as well as assembly and packaging of electronics on flexible substrates.

• Equipment development to suit the requirements of multi-component assembly on flexible and stretchable substrates, especially in roll-to-roll for both conductive adhesives and soldering.

• New selective bonding equipment based on inductive or reactive heating.

Test equipment:

• In-line and off-line technologies for the testing, validation and verification (TV&V) of heterogeneous chips and SiP with ever-increasing number of features and ever-decreasing feature size to tackle the challenge of failure localisation in these highly complex (packaged) chips.

• Characterisation equipment for quality control at multiple levels and different scales of semiconductor structures, films and components.

In addition, specific manufacturing technologies are required to enable IC-fabs with interconnected tools to support flexible, sustainable, agile and competitive high-volume semiconductor manufacturing of high- quality, advanced functionality devices and heterogeneous integration technology options in Europe. This leads to the following key focus areas:

• Enable flexible line management for high-mix and distributed manufacturing lines, including lines for fabrication and deposition of advanced functional (nano) materials.

• Enhance equipment optimised for high-volume manufacturing of large batches of the same chip into efficient reconfigurable equipment for the manufacturing of different chips in smaller batches.

• Enable productivity enhancements (e.g. wafer diameter conversions) for heterogeneous integration technologies to significantly improve cost-competitiveness.

• New manufacturing techniques combining chip and packaging technologies (e.g. chip embedding) will also require new manufacturing logistics and technologies (e.g. panel moulding).

• Adopt factory integration and control systems to address the digital industry challenge of the ECS-SRIA, and to apply fast (and deep) learning as well as semi-automated AI-based decision- making to control processes, to enhance quality, increase reliability, shorten time to stable yield, and preserve knowledge and master complexity in these innovative machine-to-machine domains.

• Apply PAD approaches with a focus on predictive maintenance, virtual metrology, factory simulation and scheduling, wafer-handling automation and the digitisation of the value chain for AI-based decision management. In addition, attention should be given to control system architecture based on machine learning: viz. predictive yield modelling, and holistic risk and decision-mastering (integrate control methods and tools and knowledge systems).

• Doubling semiconductor manufacturing in Europe in 2030 also means evolving and upgrading installed base through incremental approaches, which will necessary mean increased complexity. Managing such hybrid factories will require advanced decision support and diagnosis techniques leveraging IA but also integrating existing human knowledge and know how.

• Develop comprehensive modelling and sharing techniques to enable seamless flow and utilization of information across the whole value chain will require significant evolution of the existing knowledge management techniques and technologies (NLP to exploit existing documentation, diffusion and sharing of cutting-edge or strategic knowledge).

• Future innovations should also address new environmentally friendly solutions for manufacturing (e.g. in terms of energy consumption, chemical usage) and environmentally friendly new materials (e.g. in terms of quality, functionality, defects) in parallel with addressing the continued cost of ownership challenges. This will entail, for example, new precursors, chemicals for deposition and other wafer-processing materials, as well as gas delivery, gas handling, pumps and abatement systems. This will also comprise the study and implementation of new solutions for both effluent segregation as described above, including PFAs, as well as for water and other chemicals recycling.

To develop these future technologies, it will be key to develop dedicated equipment and manufacturing technologies for the production and characterisation of advanced integrated photonics, as well as for the production of quantum computing chips:

• In parallel with the new manufacturing/equipment technologies to suit the specific needs of integrated photonics, novel characterisation equipment and methodologies will need to be developed. These may be partly based on available technologies from electronic chip manufacturing and packaging. In addition, completely new and innovative techniques are required. Nanophotonic technologies for enhanced light–matter interaction will require the development of multi-scale fabrication and characterisation techniques suitable for dimensions ranging from a few nanometres to several centimetres. Specific equipment and processes need to be developed to enable industrial-scale fabrication of photonic ICs, such as DUV lithography and epitaxial growth of III-Vs. The hybrid combination of chips from different platforms and technology areas will also be essential to further increase functionality in the modules, and cost- effective volume packaging should therefore be a priority.

• The development of quantum computing technology will require new types of equipment, materials and manufacturing technologies. Advanced implementation options for QIP (superconducting circuits, Majorana states, etc) often require cryogenic environments and processing. Advanced industrial characterisation equipment tailored to operating in highly challenging environments will be key enablers for such developments to reach market applications. This includes new metrology equipment for mapping electrical and magnetic properties with high spatial and temporal resolution.